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8th Euromicro Conference on Digital System Design (DSD'05)
BIST Technique for GALS Systems
Porto, Portugal
August 30-September 03
ISBN: 0-7695-2433-8
Milos Krstic, IHP, Im Technologiepark
Eckhard Grass, IHP, Im Technologiepark

In this paper a test technique based on the Built-In Self- Test (BIST) is proposed. Our BIST concept is based on hierarchical testing of the digital systems. The presented test scheme is optimized for Globally Asynchronous Locally Synchronous (GALS) systems. The BIST technique, described here, is implemented on a GALS baseband processor compliant to the IEEE 802.11a standard. Some results on the performance of our test solution are given. The GALS processor with embedded BIST was fabricated in IHP?s 0.25 ?m CMOS technology and test results are presented.

Citation:
Milos Krstic, Eckhard Grass, "BIST Technique for GALS Systems," dsd, pp.10-16, 8th Euromicro Conference on Digital System Design (DSD'05), 2005
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