BIST Technique for GALS Systems

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	Similar Articles Articles by Milos Krstic Articles by Eckhard Grass

8th Euromicro Conference on Digital System Design (DSD'05)

Porto, Portugal

August 30-September 03

ISBN: 0-7695-2433-8

	ASCII Text	x
	Milos Krstic, Eckhard Grass, "BIST Technique for GALS Systems," Digital Systems Design, Euromicro Symposium on, pp. 10-16, 8th Euromicro Conference on Digital System Design (DSD'05), 2005.

	BibTex	x
	@article{ 10.1109/DSD.2005.22, author = {Milos Krstic and Eckhard Grass}, title = {BIST Technique for GALS Systems}, journal ={Digital Systems Design, Euromicro Symposium on}, volume = {0}, year = {2005}, isbn = {0-7695-2433-8}, pages = {10-16}, doi = {http://doi.ieeecomputersociety.org/10.1109/DSD.2005.22}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Digital Systems Design, Euromicro Symposium on TI - BIST Technique for GALS Systems SN - 0-7695-2433-8 SP10 EP16 A1 - Milos Krstic, A1 - Eckhard Grass, PY - 2005 KW - null VL - 0 JA - Digital Systems Design, Euromicro Symposium on ER -

Milos Krstic, IHP, Im Technologiepark

Eckhard Grass, IHP, Im Technologiepark

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DSD.2005.22

In this paper a test technique based on the Built-In Self- Test (BIST) is proposed. Our BIST concept is based on hierarchical testing of the digital systems. The presented test scheme is optimized for Globally Asynchronous Locally Synchronous (GALS) systems. The BIST technique, described here, is implemented on a GALS baseband processor compliant to the IEEE 802.11a standard. Some results on the performance of our test solution are given. The GALS processor with embedded BIST was fabricated in IHP?s 0.25 ?m CMOS technology and test results are presented.

Citation:

Milos Krstic, Eckhard Grass, "BIST Technique for GALS Systems," dsd, pp.10-16, 8th Euromicro Conference on Digital System Design (DSD'05), 2005

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