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8th Euromicro Conference on Digital System Design (DSD'05)
Automatic Design of Binary and Multiple-Valued Logic Gates on RTD Series
Porto, Portugal
August 30-September 03
ISBN: 0-7695-2433-8
Krzysztof S. Berezowski, Wroclaw University of Technology
Sarma B. K. Vrudhula, ECE Dept. University of Arizona

In this paper, we contribute to the binary and multiplevalued applications of resonant tunneling devices (RTDs). We propose a method of systematic design of physical parameters of RTD based logic. From the abstraction of their behavior, we model the design space as a handful of systems of linear inequalities generated for a given circuit topology and an arbitrary logic function. Any valid solution reflects the physical parameters assignment that implements the function given. We solve these systems using off-theshelf optimization tool and verify the results using SystemC based RTD circuit model. Our simulations confirm, that the numerical solutions are valid parameter assignments.

Citation:
Krzysztof S. Berezowski, Sarma B. K. Vrudhula, "Automatic Design of Binary and Multiple-Valued Logic Gates on RTD Series," dsd, pp.139-143, 8th Euromicro Conference on Digital System Design (DSD'05), 2005
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