Euromicro Symposium on Digital Systems Design (DSD'03) Distributing SoC Simulations over a Network of Computers Belek-Antalya, Turkey September 01-September 06 ISBN: 0-7695-2003-0
This paper presents parallelization of System-on-Chip (SoC) simulation over a network of computers. A custom C-language-based SoC exploration and simulation tool, Discrete Time Network Simulator (DTNS), is used to examine the problem. Parallelization is implemented with either CORBA or TCP/IP sockets. The distributed DTNS architecture facilitates the analysis of computation requirements for reasonable distribution. The minimum execution time per distributed process for the parallelization to be profitable is 1.2ms with CORBA and 0.4ms with TCP/IP implementation. These results are based on our networked PCs running the Linux operating system. The same network is used to evaluate this distribution method in case of video encoder SoC simulation.
Citation:
Jouni Riihim?ki, V?in? Helminen, Kimmo Kuusilinna, Timo D. H?m?l?inen, "Distributing SoC Simulations over a Network of Computers," dsd, pp.447, Euromicro Symposium on Digital Systems Design (DSD'03), 2003 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||