An Iterative Improvement Co-synthesis Algorithm for Optimization of SOPC Architecture with Dynamically Reconfigurable FPGAs

D
DSD
2003
Euromicro Symposium on Digital Systems Design (DSD'03)
Abstract - An Iterative Improvement Co-synthesis Algorithm for Optimization of SOPC Architecture with Dynamically Reconfigurable FPGAs

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Euromicro Symposium on Digital Systems Design (DSD'03)

Belek-Antalya, Turkey

September 01-September 06

ISBN: 0-7695-2003-0

	ASCII Text	x
	Radoslaw Czarnecki, Stanislaw Deniziak, Krzysztof Sapiecha, "An Iterative Improvement Co-synthesis Algorithm for Optimization of SOPC Architecture with Dynamically Reconfigurable FPGAs," Digital Systems Design, Euromicro Symposium on, pp. 443, Euromicro Symposium on Digital Systems Design (DSD'03), 2003.

	BibTex	x
	@article{ 10.1109/DSD.2003.1231980, author = {Radoslaw Czarnecki and Stanislaw Deniziak and Krzysztof Sapiecha}, title = {An Iterative Improvement Co-synthesis Algorithm for Optimization of SOPC Architecture with Dynamically Reconfigurable FPGAs}, journal ={Digital Systems Design, Euromicro Symposium on}, volume = {0}, year = {2003}, isbn = {0-7695-2003-0}, pages = {443}, doi = {http://doi.ieeecomputersociety.org/10.1109/DSD.2003.1231980}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Digital Systems Design, Euromicro Symposium on TI - An Iterative Improvement Co-synthesis Algorithm for Optimization of SOPC Architecture with Dynamically Reconfigurable FPGAs SN - 0-7695-2003-0 SP EP A1 - Radoslaw Czarnecki, A1 - Stanislaw Deniziak, A1 - Krzysztof Sapiecha, PY - 2003 KW - null VL - 0 JA - Digital Systems Design, Euromicro Symposium on ER -

Radoslaw Czarnecki, Cracow University of Technology

Stanislaw Deniziak, Cracow University of Technology

Krzysztof Sapiecha, Cracow University of Technology

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DSD.2003.1231980

In this work a HW/SW iterative improvement co-synthesis algorithm, which allows for optimization of heterogeneous system architecture with dynamically reconfigurable FPGAs is presented. The algorithm maximizes speed of the system taking into consideration cost constraints.

Citation:

Radoslaw Czarnecki, Stanislaw Deniziak, Krzysztof Sapiecha, "An Iterative Improvement Co-synthesis Algorithm for Optimization of SOPC Architecture with Dynamically Reconfigurable FPGAs," dsd, pp.443, Euromicro Symposium on Digital Systems Design (DSD'03), 2003

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