Estimating the Utilization of Embedded FPGA Co-Processor

D
DSD
2003
Euromicro Symposium on Digital Systems Design (DSD'03)
Abstract - Estimating the Utilization of Embedded FPGA Co-Processor

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Yang Qu Articles by Juha-Pekka Soininen

Euromicro Symposium on Digital Systems Design (DSD'03)

Belek-Antalya, Turkey

September 01-September 06

ISBN: 0-7695-2003-0

	ASCII Text	x
	Yang Qu, Juha-Pekka Soininen, "Estimating the Utilization of Embedded FPGA Co-Processor," Digital Systems Design, Euromicro Symposium on, pp. 214, Euromicro Symposium on Digital Systems Design (DSD'03), 2003.

	BibTex	x
	@article{ 10.1109/DSD.2003.1231929, author = {Yang Qu and Juha-Pekka Soininen}, title = {Estimating the Utilization of Embedded FPGA Co-Processor}, journal ={Digital Systems Design, Euromicro Symposium on}, volume = {0}, year = {2003}, isbn = {0-7695-2003-0}, pages = {214}, doi = {http://doi.ieeecomputersociety.org/10.1109/DSD.2003.1231929}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Digital Systems Design, Euromicro Symposium on TI - Estimating the Utilization of Embedded FPGA Co-Processor SN - 0-7695-2003-0 SP EP A1 - Yang Qu, A1 - Juha-Pekka Soininen, PY - 2003 KW - null VL - 0 JA - Digital Systems Design, Euromicro Symposium on ER -

Yang Qu, VTT Electronics

Juha-Pekka Soininen, VTT Electronics

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DSD.2003.1231929

Embedded FPGA co-processors will bring new alternatives for SoC system designers. Comparison of software implementations and reconfigurable hardware implementations will need fast and easy-to-use estimation techniques. In this paper, we present an estimation approach for the resource utilization of the embedded FPGA co-processor. Our approach is based on the principles of high-level synthesis, such as force-directed scheduling, resource allocation, operation assignment and interconnection binding. The method has been applied to simple test cases and a C-language model of MPEG-2 decoder. The average hardware estimation error of MPEG-2 functions was 25%.

Citation:

Yang Qu, Juha-Pekka Soininen, "Estimating the Utilization of Embedded FPGA Co-Processor," dsd, pp.214, Euromicro Symposium on Digital Systems Design (DSD'03), 2003

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.