A configurable memory organisation for the execution of Hiperlan/2 transceiver baseband processing and MPEG2 decoding is presented. The configuration of the memory system is done by controlling the DSP processor?s access to memory buses with an external processor and switches. The configurable memory organisation allows the scaling of system capacity to the needs of the applications and makes the use of the capacity more effective. The architecture was modelled and evaluated using a SystemC simulator and workload models. The clock frequency can be reduced by up to 25% if a configurable memory system is used instead of a bus-based shared memory. The memory latency with configurable memory organisation was less than 50% of the latency of the shared memory solution.