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Euromicro Symposium on Digital System Design (DSD'02)
A Flexible Architecture for H.263 Video Coding
Dortmund, Germany
September 04-September 06
ISBN: 0-7695-1790-0
Matias J. Garrido, Universidad Politécnica de Madrid
César Sanz, Universidad Politécnica de Madrid
Marcos Jiménez, Universidad Politécnica de Madrid
Juan M. Meneses, Universidad Politécnica de Madrid
In this paper a very flexible and efficient architecture that implements the core of a video coder according to Rec. H.263 is presented. It consists of a RISC processor that controls the scheduling of a set of specialized processors for the transforms (DCT and IDCT), quantizers (DQ and IQ), motion estimation and motion compensation (ME/MC). The architecture also includes preprocessing modules for the input video signal from the camera and interfaces for the external video memory and the H.263 bit-stream generation. The architecture has been written in synthesizable Verilog and tested using standard video sequences. It has also been prototyped into a development system based on an FPGA and a RISC.
Citation:
Matias J. Garrido, César Sanz, Marcos Jiménez, Juan M. Meneses, "A Flexible Architecture for H.263 Video Coding," dsd, pp.70, Euromicro Symposium on Digital System Design (DSD'02), 2002
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