The progress of silicon process technology relentlessly marches on. Moore's law still holds, the number of transistors that can be integrated on an IC doubles approximately every 18 months. The inability of system designs to keep up with this ever increasing number of available transistors has been debated for a long time, many solutions have been proposed. Now, as 130nm processes enter volume production, 90nm yields first engineering samples, and 65nm processes are being developed, the design productivity crisis is exacerbated by the fact that very difficult design challenges are inherent in Ultra-Deep Submicron (UDSM) technologies. They threaten the approach of abstracting technological features away at higher levels, thus endangering design productivity even more. This presentation outlines current challenges, presents approaches to address them and proposes further areas for research.