Abstract: This paper presents an implementation of a novel microprocessor architecture for executing byte compiled Java programs directly in hardware. The processor features two programming models, a Java model and a RISC model. The entities share a common data path and may operate independently although not in parallel. This combination facilitates access to hardware-near instructions and provides powerful interrupt and instruction trapping capabilities. Our processor targets medium to small embedded applications where performance in the sense of throughput is not the primary design objective, but rather the ability to execute Java code on a processor core with small die size and acceptable power consumption characteristics.