Abstract: This paper describes the development of a multiprocessor architecture that integrates data acquisition and numerical processing for a hard real-time environment. Within 3.9 ?s 15X19 ADC, samples have to be captured and analyzed. The first segment describes the function and architecture of an application-specific preprocessor that performs data acquisition and, in parallel, executes a hard-coded algorithm on the data. The second segment describes a four-way MIMD processor that works on the data prepared by the preprocessor. The architecture of the chip and critical design issues are discussed. The architecture allows the concurrent execution of multiple threads and provides efficient means for inter-thread communication. This paper focuses on the architecture and functionality. Results of the tests of the preprocessing stage are presented. Seventy-five thousand of these chips will be integrated in a highly specialized computing system for a heavy ion experiment planned to be commissioned at CERN 1 in 2005. Each chip will handle the data of 17 channels. A proto-type of the preprocessor has been implemented and tested successfully. The test of this part shows the correctness of the design. The MIMD processor is completely specified and the implementation is under way.