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Euromicro Symposium on Digital Systems Design (DSD'01)
On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization
Warsaw, Poland
September 04-September 06
ISBN: 0-7695-1239-9
ASCII Text
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Enrique San Millán, Luis Entrena, José Alberto Espejo, "On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization," Digital Systems Design, Euromicro Symposium on, pp. 0292, Euromicro Symposium on Digital Systems Design (DSD'01), 2001.
 
 
BibTex
x
 
@article{ 10.1109/DSD.2001.952305,
author = {Enrique San Millán and Luis Entrena and José Alberto Espejo},
title = {On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization},
journal ={Digital Systems Design, Euromicro Symposium on},
volume = {0},
year = {2001},
isbn = {0-7695-1239-9},
pages = {0292},
doi = {http://doi.ieeecomputersociety.org/10.1109/DSD.2001.952305},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Digital Systems Design, Euromicro Symposium on
TI - On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization
SN - 0-7695-1239-9
SP
EP
A1 - Enrique San Millán,
A1 - Luis Entrena,
A1 - José Alberto Espejo,
PY - 2001
VL - 0
JA - Digital Systems Design, Euromicro Symposium on
ER -
 
Enrique San Millán, University Carlos III of Madrid
Luis Entrena, University Carlos III of Madrid
José Alberto Espejo, University Carlos III of Madrid
Abstract: This paper attempts to determine the capabilities of existing Redundancy Addition and Removal (SRAR) techniques for logic optimization of sequential circuits. To this purpose, we compare this method with the Retiming and Resynthesis (RaR) techniques. For the RaR case the set of possible transformations has been established by relating them to STG transformations by other authors. Following these works, we first formally demonstrate that logic transformations provided by RaR are covered by SRAR as well. Then we also show that SRAR is able to identify transformations that cannot be found by RaR. This way we prove the higher potential of the Sequential Redundancy Addition and Removal over the Retiming and Resynthesis techniques.
Citation:
Enrique San Millán, Luis Entrena, José Alberto Espejo, "On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization," dsd, pp.0292, Euromicro Symposium on Digital Systems Design (DSD'01), 2001
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