Euromicro Symposium on Digital Systems Design (DSD'01) Regular Realization of Symmetric Functions Using Reversible Logic Warsaw, Poland September 04-September 06 ISBN: 0-7695-1239-9
Abstract: Reversible logic is of increasing importance to many future computer technologies. We introduce a regular structure to realize symmetric functions in binary reversible logic. This structure, called a 2 * 2 net structure, allows for a more efficient realization of symmetric functions than the methods introduced by the other authors. Our synthesis method allows us to realize arbitrary symmetric function in a completely regular structure of reversible gates with relatively little "garbage". Because every Boolean function can be made symmetric by repeating input variables, our method is applicable to arbitrary multi-input multi-output Boolean functions and realizes such arbitrary function in a circuit with a relatively small number of additional gate outputs. The method can be also used in classical logic. Its advantages in terms of numbers of gates and inputs/outputs are especially seen for symmetric or incompletely specified functions with many outputs.
Citation:
Marek Perkowski, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Xiaoyu Song, Anas Al-Rabadi, Bart Massey, Pawel Kerntopf, Andrzej Buller, Lech Jozwiak, Alan Coppola, "Regular Realization of Symmetric Functions Using Reversible Logic," dsd, pp.0245, Euromicro Symposium on Digital Systems Design (DSD'01), 2001 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||