Abstract: Making gate arrays obsolete. FPGAs are successfully proceeding from niche to mainstream. Like microprocessor usage, FPGA application is RAM-based, but by structural programming (also called "(re)configuration") instead of procedural programming. Now both, host and accelerator are RAM-based and as such also available on the same chip: a new approach to SoC Design. Now also accelerator definition may be-at least partly-conveyed from vendor site to customer site. A new business model is needed. But this paradigm switch is still ignored: FPGAs do not repeat the RAM-based success story of the software industry. There is not yet a configurable industry, since mapping applications onto FPGAs mainly uses hardware synthesis methods. From a decade of world-wide research on Reconfigurable Computing another breed of reconfigurable platforms is an emerging future competitor to FPGAs. Supporting roughly single bit wide configurable logic blocks (CLBs) the mapping tools are mainly based on gate level methods-similar to CAD for hardwired logic. In contrast to this fine-grained reconfigurability, the Reconfigurable datapath units (rDPUs) with drastically reduced reconfigurability overhead: to directly configure high level parallelism. But the "von Neumann" paradigm does not support soft datapaths because "instruction fetch" is not done at run time, and, since most reconfigurable computing arrays do not run parallel processes, but multiple pipe networks instead. To introduce the new business model to cope with the current accelerator design crisis a transition from CAD to complication configuration/software co-compilation. The paper illustrates such a roadmap to reconfigurable computing, supporting the emerging trend to platform-based SoC design.