Abstract: Modern circuit implementation technologies (FPGAs, CPWs, complex gates, etc.) introduce new implementation constraints and optimization criteria to sequential circuit synthesis. Moreover; to ensure good quality results, these criteria need to be applied throughout the entire circuit synthesis process, starting at state encoding. In this paper; we present new methods and tools for state encoding and combinational synthesis of sequential circuits based on new criteria of information flow optimization. Together; they form a unified and complete pre-placement synthesis chain. Experimental results indicate that the unified, information-driven approach is effective, resulting in circuits from IWLS benchmark being on average 25% smaller and 30% faster than those synthesized by another state-of-the-art tools.