20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05) Transient Behavior of the Encoding/Decoding Circuits of Error Correcting Codes Monterey, California October 03-October 05 ISBN: 0-7695-2464-8
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFTVS.2005.67
In this paper, we present an in-depth analysis of transient behavior, mainly glitches, in the parallel encoding and decoding circuits of error correcting codes. First, we found that the probability of a given number of glitches that may accumulate in the encoding/decoding circuit exhibits a Gaussianlike distribution. An estimation methodology was developed so the transient behavior of an ECC for very long word length can be predicted. We confirm that the principle of minimum-equal-weight construction of H-matrix is the best design strategy. Two potential solutions are proposed and examined to reduce the accumulation of glitches. Finally, we present the calculation methods and provide examples of odd-weight-column SEC-DED codes for up to 1024 information bits.
Citation:
Jien-Chung Lo, Yu-Lun Wan, Eiji Fujiwara, "Transient Behavior of the Encoding/Decoding Circuits of Error Correcting Codes," dft, pp.120-130, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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