20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05) Test of Interconnection Opens Considering Coupling Signals Monterey, California October 03-October 05 ISBN: 0-7695-2464-8
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFTVS.2005.64
In this work a strategy to improve the detectability of interconnection open defects applying proper logic levels at the coupled lines is proposed. A framework called OPVEG which uses layout information and a commercial ATPG under the stuck-at model has been developed. Those signal values at the coupled lines which favor the detection of the opens using a boolean based test are attempted to be generated. The strategy is applied to four ISCAS?85 benchmark circuits. It has been found that a significant number of considered coupled signals can be forced to a proper logic value. Hence, the likelihood of detection of interconnection opens is increased. Furthermore, those lines di?cult to test are identified.
Citation:
Roberto Gomez, Alejandro Giron, Victor Champac, "Test of Interconnection Opens Considering Coupling Signals," dft, pp.247-258, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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