20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05) Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment Monterey, California October 03-October 05 ISBN: 0-7695-2464-8
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFTVS.2005.60
This paper presents a new test methodology which utilizes the Programming Language Interface (PLI) for performing fault simulation of combinational or full scan Intellectual Property (IP) core-based designs for System-on-Chip (SOC). Using the latest Verilog PLI, referred to as Verilog Procedural Interface (VPI), critical-path tracing and two-value deductive fault simulations are performed on a pre-compiled core basis as available in a simulator s intermediate format. By applying this VPI-based test methodology on ISCAS85 Verilog benchmarks results are presented in terms of elapsed simulation time and fault coverage for stuck-at faults and improvement over previous works is reported.
Citation:
Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi, "Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment," dft, pp.389-397, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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