Scan test has been a common and useful method for testing VLSI designs due to the high controllability and observability it provides. These same properties have recently been shown to also be a security threat to the intellectual property on a chip [1]. In order to defend from scan based attacks, we present the Lock & Key technique. Our proposed technique provides security while not negatively impacting the design?s fault coverage. This technique requires only that a small area overhead penalty is incurred for a significant return in security. Lock & Key divides the already present scan chain into smaller subchains of equal length that are controlled by an internal test security controller. When a malicious user attempts to manipulate the scan chain, the test security controller goes into insecure mode and enables each subchain in an unpredictable sequence making controllability and observability of the circuit under test very difficult. We will present and analyze the design of the Lock & Key technique to show that this is a flexible option to secure scan designs for various levels of security.