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20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)
On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits
Monterey, California
October 03-October 05
ISBN: 0-7695-2464-8
ASCII Text
x 
 
J. Di, P.K. Lala, D. Vasudevan, "On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits," Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on, pp. 371-379, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005.
 
 
BibTex
x
 
@article{ 10.1109/DFTVS.2005.51,
author = {J. Di and P.K. Lala and D. Vasudevan},
title = {On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits},
journal ={Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on},
volume = {0},
year = {2005},
isbn = {0-7695-2464-8},
pages = {371-379},
doi = {http://doi.ieeecomputersociety.org/10.1109/DFTVS.2005.51},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
TI - On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits
SN - 0-7695-2464-8
SP371
EP379
A1 - J. Di,
A1 - P.K. Lala,
A1 - D. Vasudevan,
PY - 2005
KW - null
VL - 0
JA - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
ER -
 
J. Di, University of Arkansas
P.K. Lala, University of Arkansas
D. Vasudevan, University of Arkansas

Nanocomputing system design has been attracting attention in recent years. Regular structure and reliable timing control are the two requirements to implement nanoscale circuits. A cellular array has highly regular structure. The cells are adjacent to each other and are able to process signals based on simple transition rules. In delay-insensitive circuits the delay on a signal path does not affect circuit behavior. The combination of delayinsensitive circuits and cellular arrays make it feasible to implement silicon-based nanoscale circuits. However, little work has been done on the test of such circuits. This paper provides a complete analysis of the effect of stuck-at faults in delay-insensitive circuits on cellular arrays.

Citation:
J. Di, P.K. Lala, D. Vasudevan, "On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits," dft, pp.371-379, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005
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