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20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)
On Generating Pseudo-Functional Delay Fault Tests for Scan Designs
Monterey, California
October 03-October 05
ISBN: 0-7695-2464-8
ASCII Text
x 
 
Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, "On Generating Pseudo-Functional Delay Fault Tests for Scan Designs," Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on, pp. 398-405, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005.
 
 
BibTex
x
 
@article{ 10.1109/DFTVS.2005.49,
author = {Zhuo Zhang and Sudhakar M. Reddy and Irith Pomeranz},
title = {On Generating Pseudo-Functional Delay Fault Tests for Scan Designs},
journal ={Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on},
volume = {0},
year = {2005},
isbn = {0-7695-2464-8},
pages = {398-405},
doi = {http://doi.ieeecomputersociety.org/10.1109/DFTVS.2005.49},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
TI - On Generating Pseudo-Functional Delay Fault Tests for Scan Designs
SN - 0-7695-2464-8
SP398
EP405
A1 - Zhuo Zhang,
A1 - Sudhakar M. Reddy,
A1 - Irith Pomeranz,
PY - 2005
KW - null
VL - 0
JA - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
ER -
 
Zhuo Zhang, University of Iowa
Sudhakar M. Reddy, University of Iowa
Irith Pomeranz, Purdue University

In designs using DFT such as scan some of the faults that are untestable in the circuit without DFT become testable after DFT insertion. Additionally, scan tests may scan in illegal or unreachable states that cause non-functional operation of the circuit during test. This may cause higher than normal power dissipation and demands on supply current. We propose new techniques to determine illegal states of circuits that can be used during ATPG to prohibit tests using such states. The resulting tests are essentially functional or pseudo-functional.

Citation:
Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, "On Generating Pseudo-Functional Delay Fault Tests for Scan Designs," dft, pp.398-405, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005
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