Methodologies and Algorithms for Testing Switch-Based NoC Interconnects

D
DFT
2005
20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)
Abstract - Methodologies and Algorithms for Testing Switch-Based NoC Interconnects

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Cristian Grecu Articles by Partha Pande Articles by Baosheng Wang Articles by Andr? Ivanov Articles by Res Saleh

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)

Monterey, California

October 03-October 05

ISBN: 0-7695-2464-8

	ASCII Text	x
	Cristian Grecu, Partha Pande, Baosheng Wang, Andr? Ivanov, Res Saleh, "Methodologies and Algorithms for Testing Switch-Based NoC Interconnects," Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on, pp. 238-246, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005.

	BibTex	x
	@article{ 10.1109/DFTVS.2005.45, author = {Cristian Grecu and Partha Pande and Baosheng Wang and Andr? Ivanov and Res Saleh}, title = {Methodologies and Algorithms for Testing Switch-Based NoC Interconnects}, journal ={Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on}, volume = {0}, year = {2005}, isbn = {0-7695-2464-8}, pages = {238-246}, doi = {http://doi.ieeecomputersociety.org/10.1109/DFTVS.2005.45}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on TI - Methodologies and Algorithms for Testing Switch-Based NoC Interconnects SN - 0-7695-2464-8 SP238 EP246 A1 - Cristian Grecu, A1 - Partha Pande, A1 - Baosheng Wang, A1 - Andr? Ivanov, A1 - Res Saleh, PY - 2005 KW - null VL - 0 JA - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on ER -

Cristian Grecu, University of British Columbia

Partha Pande, University of British Columbia

Baosheng Wang, University of British Columbia

Andr? Ivanov, University of British Columbia

Res Saleh, University of British Columbia

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFTVS.2005.45

In this paper, we present two novel methodologies for testing the interconnect fabrics of network-on-chip (NoC) based chips. Both use the concept of recursive testing, with different degrees of parallelism in each case. Our test methodologies cover the logic switching blocks and the FIFO buffers that are the basic components of NoC fabrics. The paper concludes with test time evaluations for different NoC topologies and sizes.

Citation:

Cristian Grecu, Partha Pande, Baosheng Wang, Andr? Ivanov, Res Saleh, "Methodologies and Algorithms for Testing Switch-Based NoC Interconnects," dft, pp.238-246, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.