Efficient Failure Detection in Pipelined Asynchronous Circuits

D
DFT
2005
20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)
Abstract - Efficient Failure Detection in Pipelined Asynchronous Circuits

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Song Peng Articles by Rajit Manohar

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)

Monterey, California

October 03-October 05

ISBN: 0-7695-2464-8

	ASCII Text	x
	Song Peng, Rajit Manohar, "Efficient Failure Detection in Pipelined Asynchronous Circuits," Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on, pp. 484-493, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005.

	BibTex	x
	@article{ 10.1109/DFTVS.2005.33, author = {Song Peng and Rajit Manohar}, title = {Efficient Failure Detection in Pipelined Asynchronous Circuits}, journal ={Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on}, volume = {0}, year = {2005}, isbn = {0-7695-2464-8}, pages = {484-493}, doi = {http://doi.ieeecomputersociety.org/10.1109/DFTVS.2005.33}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on TI - Efficient Failure Detection in Pipelined Asynchronous Circuits SN - 0-7695-2464-8 SP484 EP493 A1 - Song Peng, A1 - Rajit Manohar, PY - 2005 KW - null VL - 0 JA - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on ER -

Song Peng, Cornell University

Rajit Manohar, Cornell University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFTVS.2005.33

This paper presents an efficient concurrent failure detection method for pipelined asynchronous circuits. We first validate permanent and transient fault modeling in clockless systems. By augmenting the rails to each data channel and adding extra logic to each circuit module, we make pipelined asynchronous circuits achieve fail-stop with respect to hard or soft errors. The experimental evaluations show this method incurs both reasonable hardware cost and low performance overhead.

Citation:

Song Peng, Rajit Manohar, "Efficient Failure Detection in Pipelined Asynchronous Circuits," dft, pp.484-493, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.