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20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)
Design of a CMOS Operational Amplifier Amenable to Extreme Voltage Stress
Monterey, California
October 03-October 05
ISBN: 0-7695-2464-8
ASCII Text
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Shaolei Quan, Meng-Yao Liu, Chin-Long Wey, "Design of a CMOS Operational Amplifier Amenable to Extreme Voltage Stress," Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on, pp. 563-572, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005.
 
 
BibTex
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@article{ 10.1109/DFTVS.2005.31,
author = {Shaolei Quan and Meng-Yao Liu and Chin-Long Wey},
title = {Design of a CMOS Operational Amplifier Amenable to Extreme Voltage Stress},
journal ={Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on},
volume = {0},
year = {2005},
isbn = {0-7695-2464-8},
pages = {563-572},
doi = {http://doi.ieeecomputersociety.org/10.1109/DFTVS.2005.31},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
TI - Design of a CMOS Operational Amplifier Amenable to Extreme Voltage Stress
SN - 0-7695-2464-8
SP563
EP572
A1 - Shaolei Quan,
A1 - Meng-Yao Liu,
A1 - Chin-Long Wey,
PY - 2005
KW - null
VL - 0
JA - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
ER -
 
Shaolei Quan, Michigan State University, USA
Meng-Yao Liu, Natinal Central University, Taiwan
Chin-Long Wey, Natinal Central University, Taiwan

Extreme voltage stress (EVS) is an attractive burn-in technique employed in production test to weed out weak chips that may cause infant mortality. Application of this technique to analog integrated circuit (IC) has, however, only achieved limited success due to the significant irregularity in circuit topology. This paper examines the issue of design for EVS in analog IC and presents several analog circuit structures use of which enhances voltage stressability of analog circuits. Based on proposed circuit concepts an operational amplifier is designed in TSMC 0.18?m CMOS technology and is simulated with HSPICE. Simulation results have shown that the designed operational amplifier is fully stressable with slight performance degradation.

Citation:
Shaolei Quan, Meng-Yao Liu, Chin-Long Wey, "Design of a CMOS Operational Amplifier Amenable to Extreme Voltage Stress," dft, pp.563-572, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005
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