Delay testing based on transition faults propagated to all reachable outputs (TARO) is more effective in detecting defective chips compared to conventional transition faults. This paper describes efficient approaches to generate delay tests pattern based on TARO metric using Boolean Satisfiability (SAT). Different excitation paths are activated when multiple vectors are required for TARO propagation (N-detect) for better coverage of unmodeled faults. An efficient TARO test compaction method is also presented. Experimental results on several benchmarks show the effectiveness of this ATPG technique. Specifically, the increase in the number of test patterns due to using our TARO ATPG instead of transition fault testing (31%) is much smaller than previous TARO test generation techniques (2200%).