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20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)
Defects, Yield, and Design in Sublithographic Nano-electronics
Monterey, California
October 03-October 05
ISBN: 0-7695-2464-8
ASCII Text
x 
 
Mehdi B. Tahoori, "Defects, Yield, and Design in Sublithographic Nano-electronics," Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on, pp. 3-11, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005.
 
 
BibTex
x
 
@article{ 10.1109/DFTVS.2005.28,
author = {Mehdi B. Tahoori},
title = {Defects, Yield, and Design in Sublithographic Nano-electronics},
journal ={Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on},
volume = {0},
year = {2005},
isbn = {0-7695-2464-8},
pages = {3-11},
doi = {http://doi.ieeecomputersociety.org/10.1109/DFTVS.2005.28},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
TI - Defects, Yield, and Design in Sublithographic Nano-electronics
SN - 0-7695-2464-8
SP3
EP11
A1 - Mehdi B. Tahoori,
PY - 2005
KW - null
VL - 0
JA - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
ER -
 
Mehdi B. Tahoori, Northeastern University, Boston, MA

It is anticipated that defect densities in bottom-up self-assembled nanotechnology are much higher than those in conventional VLSI technologies. Therefore, defect tolerance needs to be included in various steps of the design automation flow. In this paper, a new defect tolerant flow is proposed and a new yield metric, based on this flow, is defined. This metric is evaluated for various molecular crossbars with different defect densities. Test and diagnosis of molecular crossbars, as the main building blocks in this technology, are also investigated.

Citation:
Mehdi B. Tahoori, "Defects, Yield, and Design in Sublithographic Nano-electronics," dft, pp.3-11, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005
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