20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05) Defect Tolerance for Molecular Electronics-Based NanoFabrics Using Built-In Self-Test Procedure Monterey, California October 03-October 05 ISBN: 0-7695-2464-8
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFTVS.2005.27
A BIST procedure is proposed for testing and fault tolerance of molecular electronics-based nanoFabrics. The nanoFabrics are assumed to include up to 1010 gates; this requires new test strategies that can efficiently test and diagnose the nanoFabric in a reasonable time. Our BIST procedure utilizes nanoFabric?s components as test pattern generator and response analyzer. The proposed technique tests the components in parallel with a low number of test configurations reducing the test time significantly. Due to high defect density of nanoFabrics, a diagnostic procedure needs to be done to achieve a high recovery. A defect database is created to be used by compilers during configuring the nanoFabric to avoid defective components. This results in a reliable system constructed using unreliable components.
Citation:
Mohammad Tehranipoor, "Defect Tolerance for Molecular Electronics-Based NanoFabrics Using Built-In Self-Test Procedure," dft, pp.305-313, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||