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20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)
An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors
Monterey, California
October 03-October 05
ISBN: 0-7695-2464-8
ASCII Text
x 
 
P. Bernardi, L. Bolzani, M. Rebaudengo, M. Sonza Reorda, M. Violante, "An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors," Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on, pp. 445-453, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005.
 
 
BibTex
x
 
@article{ 10.1109/DFTVS.2005.17,
author = {P. Bernardi and L. Bolzani and M. Rebaudengo and M. Sonza Reorda and M. Violante},
title = {An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors},
journal ={Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on},
volume = {0},
year = {2005},
isbn = {0-7695-2464-8},
pages = {445-453},
doi = {http://doi.ieeecomputersociety.org/10.1109/DFTVS.2005.17},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
TI - An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors
SN - 0-7695-2464-8
SP445
EP453
A1 - P. Bernardi,
A1 - L. Bolzani,
A1 - M. Rebaudengo,
A1 - M. Sonza Reorda,
A1 - M. Violante,
PY - 2005
KW - null
VL - 0
JA - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
ER -
 
P. Bernardi, Politecnico di Torino
L. Bolzani, Politecnico di Torino
M. Rebaudengo, Politecnico di Torino
M. Sonza Reorda, Politecnico di Torino
M. Violante, Politecnico di Torino

Software Implemented Hardware Fault Tolerance (SIHFT) techniques are able to detect most of the transient and permanent faults during the usual system operations. However, these techniques are not capable to detect some transient faults affecting processor memory elements such as state registers inside the processor control unit, or temporary registers inside the arithmetic and logic unit. In this paper we propose an integrated (hardware and software) approach to increase the fault detection capabilities of software techniques by introducing a limited hardware redundancy. Experimental results are reported showing the effectiveness of the proposed approach in covering soft-errors affecting the processor memory elements and escaping to purely software approaches.

Citation:
P. Bernardi, L. Bolzani, M. Rebaudengo, M. Sonza Reorda, M. Violante, "An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors," dft, pp.445-453, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005
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