20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05) A Technique for Modular Design of Self-Checking Carry-Select Adder Monterey, California October 03-October 05 ISBN: 0-7695-2464-8
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFTVS.2005.15
The carry-select adders provide significant speed improvement over other types of adders. This paper proposes a new approach for constructing self-checking carry-select adders of arbitrary size. The scheme is illustrated with the implementation of a 2-bit carry select adder that can detect a pre-determined set of faults online. Adders of arbitrary size can be constructed by simply cascading the appropriate number of 2-bit adders. A range of adders from 4 bit to 128 bits was designed using this approach employing a 0.5? CMOS technology. The area needed for implementing the self-checking adders is 16.07% to 20.67% more than that required in adders without built-in self-checking capability.
Citation:
D. P. Vasudevan, P. K. Lala, "A Technique for Modular Design of Self-Checking Carry-Select Adder," dft, pp.325-333, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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