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20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)
A New Test Methodology For DNL Error In Flash ADC?s
Monterey, California
October 03-October 05
ISBN: 0-7695-2464-8
ASCII Text
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Michael Wieckowski, John Liobe, Quentin Diduck, Martin Margala, "A New Test Methodology For DNL Error In Flash ADC?s," Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on, pp. 582-590, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005.
 
 
BibTex
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@article{ 10.1109/DFTVS.2005.11,
author = {Michael Wieckowski and John Liobe and Quentin Diduck and Martin Margala},
title = {A New Test Methodology For DNL Error In Flash ADC?s},
journal ={Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on},
volume = {0},
year = {2005},
isbn = {0-7695-2464-8},
pages = {582-590},
doi = {http://doi.ieeecomputersociety.org/10.1109/DFTVS.2005.11},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
TI - A New Test Methodology For DNL Error In Flash ADC?s
SN - 0-7695-2464-8
SP582
EP590
A1 - Michael Wieckowski,
A1 - John Liobe,
A1 - Quentin Diduck,
A1 - Martin Margala,
PY - 2005
KW - null
VL - 0
JA - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
ER -
 
Michael Wieckowski, University of Rochester
John Liobe, University of Rochester
Quentin Diduck, University of Rochester
Martin Margala, University of Rochester

A novel test methodology is presented for characterizing DNL error in Flash analog to digital converters. This test technique accurately measures the resistance of each resistor in the Flash ladder and in turn, characterizes the DNL of a given chip. A testing time of approximately ms is achieved with a 30% increase in area for a 6-bit Flash ADC. When used in conjunction with standard automated test equipment, a reduction in total testing time and cost is predicted with minimal increase in area and power overhead.

Citation:
Michael Wieckowski, John Liobe, Quentin Diduck, Martin Margala, "A New Test Methodology For DNL Error In Flash ADC?s," dft, pp.582-590, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005
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