Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture

D
DFT
2003
18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03)
Abstract - Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture

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	Similar Articles Articles by Shervin Sharifi Articles by Mohammad Hosseinabadi Articles by Pedram Riahi Articles by Zainalabedin Navabi

18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03)

Boston, Massachusetts

November 03-November 05

ISBN: 0-7695-2042-1

	ASCII Text	x
	Shervin Sharifi, Mohammad Hosseinabadi, Pedram Riahi, Zainalabedin Navabi, "Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture," Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on, pp. 352, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003.

	BibTex	x
	@article{ 10.1109/DFTVS.2003.1250131, author = {Shervin Sharifi and Mohammad Hosseinabadi and Pedram Riahi and Zainalabedin Navabi}, title = {Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture}, journal ={Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on}, volume = {0}, year = {2003}, issn = {1063-6722}, pages = {352}, doi = {http://doi.ieeecomputersociety.org/10.1109/DFTVS.2003.1250131}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on TI - Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture SN - 1063-6722 SP EP A1 - Shervin Sharifi, A1 - Mohammad Hosseinabadi, A1 - Pedram Riahi, A1 - Zainalabedin Navabi, PY - 2003 KW - null VL - 0 JA - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on ER -

Shervin Sharifi, University of Tehran

Mohammad Hosseinabadi, University of Tehran

Pedram Riahi, Northeastern University

Zainalabedin Navabi, University of Tehran

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFTVS.2003.1250131

Time, power and data volume are among the most challenging problems in test of System-on- Chip (SoC) devices. These problems become even more important in scan-based test. The Selective Trigger Scan architecture introduced in this paper addresses these problems. This architecture reduces switching activity in circuit-under-test (CUT) and increases the scan clock frequency. Format of data for this reduced activity architecture enables us to perform a good compression and further reduce the test time. Our experiments on ISCAS 85 and 89 benchmark circuits show effectiveness of this architecture in improving SoC test in terms of power, time and data volume.

Citation:

Shervin Sharifi, Mohammad Hosseinabadi, Pedram Riahi, Zainalabedin Navabi, "Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture," dft, pp.352, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003

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