Hybrid BIST Using an Incrementally Guided LFSR

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	Similar Articles Articles by C.V. Krishna Articles by Nur A. Touba

18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03)

Boston, Massachusetts

November 03-November 05

ISBN: 0-7695-2042-1

	ASCII Text	x
	C.V. Krishna, Nur A. Touba, "Hybrid BIST Using an Incrementally Guided LFSR," Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on, pp. 217, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003.

	BibTex	x
	@article{ 10.1109/DFTVS.2003.1250115, author = {C.V. Krishna and Nur A. Touba}, title = {Hybrid BIST Using an Incrementally Guided LFSR}, journal ={Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on}, volume = {0}, year = {2003}, issn = {1063-6722}, pages = {217}, doi = {http://doi.ieeecomputersociety.org/10.1109/DFTVS.2003.1250115}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on TI - Hybrid BIST Using an Incrementally Guided LFSR SN - 1063-6722 SP EP A1 - C.V. Krishna, A1 - Nur A. Touba, PY - 2003 KW - null VL - 0 JA - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on ER -

C.V. Krishna, University of Texas at Austin

Nur A. Touba, University of Texas at Austin

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFTVS.2003.1250115

A new hybrid BIST scheme is proposed which is based on using an "incrementally guided LFSR." It very efficiently combines external deterministic data from the tester with on-chip pseudo-random BIST. The hardware overhead is very small as a conventional STUMPS architecture [1] is used with only a small modification to the feedback of the LFSR which allows the tester to incrementally guide the LFSR so that it can embed patterns that detect the random-pattern-resistant faults in the pseudo-random sequence. Compared with external testing, the proposed approach achieves dramatic reductions in tester storage requirements while using very simple on-chip hardware. Results indicate that the proposed approach provides very attractive tradeoffs between test length and tester storage requirements.

Citation:

C.V. Krishna, Nur A. Touba, "Hybrid BIST Using an Incrementally Guided LFSR," dft, pp.217, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003

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