The mixed static-dynamic circuits are widely used to design high-performance circuits (e.g. ALU, communication circuit etc), among them the most famous one is the True Single-Phase Clocked (TSPC) dynamic circuits. The TSPC is often used to design high-speed dynamic-sequential CMOS circuits, which contain dynamic, static circuits and memory elements (such as latches, and flip-flops). All these components are operated in a single clocking phase system. Although the scan design is an applicable technique for most circuits, especially for the Intellectual Property (IP) design, scan testing issues for mixed dynamic/static circuit themselves are seldom discussed. In this paper, we propose a new design of scan latch and full/partial scan test strategy for single phase dynamic TSPC circuits, which are constructed by N (P) type of domino logic and clock latches. The full-scan deign could support circuit diagnosis capability while the partial-scan would lead to less performance penalty.