2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points Chicago, Illinois October 07-October 09 ISBN: 978-0-7695-3839-6
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFT.2009.33
Recently, a new test point insertion method for pseudo-random built-in self-test (BIST) was proposed in [Yang 09] which tries to use functional flip-flops to drive control test points instead of adding extra dedicated flip-flops for driving the control points. This paper investigates methods to further reduce the area overhead by replacing dedicated flip-flops which could not be replaced in [Yang 09]. A new algorithm (alternative selection algorithm) is proposed to find candidate flip-flops out of the fan-in cone of a test point. Experimental results indicate that most of the not-replaced flip-flops in [Yang 09] can be replaced and hence even more significant area reduction can be achieved with minimizing the loss of testability.
Index Terms:
BIST, Test Point Insertion, Alternative Selection Algorithm, Use of Functional Flip-Flops to Drive Control Points
Citation:
Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba, "Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points," dft, pp.20-28, 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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