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22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)
Sensitivity evaluation of TMR-hardened circuits to multiple SEUs induced by alpha particles in commercial SRAM-based FPGAs
Rome, Italy
September 26-September 28
ISBN: 0-7695-2885-6
A. Manuzzato, Università di Padova
P. Rech, Università di Padova
S. Gerardin, Università di Padova
A. Paccagnella, Università di Padova
L. Sterpone, Politecnico di Torino
M. Violante, Politecnico di Torino
We present an experimental analysis of the sensitivity of SRAM-based FPGAs to alpha particles. We study how the different resources inside the FPGA (LUTs, MUXs, PIPs, etc. ) are affected by alpha-induced SEUs, assessing the cross section for the configuration memory cells controlling each of them. We then show two case studies, a chain of FIR filters and a series of soft microcontrollers implemented in the FPGA, measuring the rate of functional interruptions during exposure to a constant flux of alpha particles. The designs are then hardened using triplication with a single final voter, with intermediate voters, and finally including also feedback voters. The robustness of each hardening solution is discussed, analyzing the trade-off between area and fault-tolerance as a function of the number of SEUs in the configuration memory. An analytical model to predict the cross section of a given design with and without hardening solutions is finally proposed, starting from the experimental data.
Citation:
A. Manuzzato, P. Rech, S. Gerardin, A. Paccagnella, L. Sterpone, M. Violante, "Sensitivity evaluation of TMR-hardened circuits to multiple SEUs induced by alpha particles in commercial SRAM-based FPGAs," dft, pp.79-86, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
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