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22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)
An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains
Rome, Italy
September 26-September 28
ISBN: 0-7695-2885-6
ASCII Text
x 
 
J. Lagos-Benites, D. Appello, P. Bernardi, M. Grosso, D. Ravotto, E. Sánchez, M. Sonza Reorda, "An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains," Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on, pp. 291-302, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007.
 
 
BibTex
x
 
@article{ 10.1109/DFT.2007.47,
author = {J. Lagos-Benites and D. Appello and P. Bernardi and M. Grosso and D. Ravotto and E. Sánchez and M. Sonza Reorda},
title = {An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains},
journal ={Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on},
volume = {0},
year = {2007},
isbn = {0-7695-2885-6},
pages = {291-302},
doi = {http://doi.ieeecomputersociety.org/10.1109/DFT.2007.47},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
TI - An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains
SN - 0-7695-2885-6
SP291
EP302
A1 - J. Lagos-Benites,
A1 - D. Appello,
A1 - P. Bernardi,
A1 - M. Grosso,
A1 - D. Ravotto,
A1 - E. Sánchez,
A1 - M. Sonza Reorda,
PY - 2007
KW - null
VL - 0
JA - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
ER -
 
J. Lagos-Benites, Pontificia Universidad Católica del Perú, Lima, Perú
D. Appello, STMicroelectronics, Milano, Italy
P. Bernardi, Politecnico di Torino, Torino, Italy
M. Grosso, Politecnico di Torino, Torino, Italy
D. Ravotto, Politecnico di Torino, Torino, Italy
E. Sánchez, Politecnico di Torino, Torino, Italy
M. Sonza Reorda, Politecnico di Torino, Torino, Italy

In this paper, a Software-Based Diagnosis (SBD) procedure suitable for SoCs is proposed to tackle the diagnosis of transition-delay faults. The illustrated methodology takes advantage of an initial Software-Based Self-Test (SBST) test set and of the scan-chains included in the final SoC design release. In principle, the proposed methodology consists in partitioning the considered SBST test set in several slices, and then proceeding to the evaluation of the diagnostic ability owned by each slice with the aim of discarding diagnosis-ineffective test programs portions.

The proposed methodology is aimed to provide precise feedback to the failure analysis process focusing the systematic timing failures characteristic of new technologies. Experimental results show the effectiveness and feasibility of the proposed approach on a suitable SoC test vehicle including an 8-bit microcontroller, 4 SRAM memories and an arithmetic core, manufactured by STMicroelectronics, whose purpose is to provide precise information to the failure analysis process. The reached diagnostic resolution is up to the 99.75%, compared to the 93.14% guaranteed by the original SBST procedure.

Citation:
J. Lagos-Benites, D. Appello, P. Bernardi, M. Grosso, D. Ravotto, E. Sánchez, M. Sonza Reorda, "An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains," dft, pp.291-302, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
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