22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) Hierarchical Fault Compatibility Identification for Test Generation with a Small Number of Specified Bits Rome, Italy September 26-September 28 ISBN: 0-7695-2885-6
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFT.2007.46
Identification of bits that do not necessarily have to be specified in a test set can be beneficial to a number of applications, including low power test, test set encoding and embedding, and test set enriching with n-detect or other fault types properties. This work presents a new method for generating tests containing only a small number of specified bits, while keeping the number of total tests small. The method relies on finding a large number of faults that can be detected by a single test (compatible faults) with a small number of specified bits. Both the total number of specified bits in the test set as well as the number of specified bits per test are minimized. The obtained experimental results show that the proposed methodology can generate compact test sets with an average of 60% of unspecified bits, outperforming existing methods that consider this problem.
Citation:
Stelios Neophytou, Maria K. Michael, "Hierarchical Fault Compatibility Identification for Test Generation with a Small Number of Specified Bits," dft, pp.439-447, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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