22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) Testing of Asynchronous NULL Conventional Logic (NCL) Circuits in Synchronous-Based Desig Rome, Italy September 26-September 28 ISBN: 0-7695-2885-6
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFT.2007.40
Conventional Automatic Test Pattern Generation (ATPG) algorithms would fail when applied to asynchronous circuits due to the absence of a global clock and presence of more state holding elements that synchronize the control and data paths, leading to poor fault coverage. This paper presents a Design for Test (DFT) approach aimed at making asynchronous NCL circuits testable using conventional ATPG tools when incorporated with synchronous-based designs. The proposed approach performs scan and test points insertion on NCL designs using custom ATPG library. Experimental results show significant increase in fault coverage for NCL cyclic and acyclic pipelined designs.
Citation:
Waleed K. Al-Assadi, Sindhu Kakarla, "Testing of Asynchronous NULL Conventional Logic (NCL) Circuits in Synchronous-Based Desig," dft, pp.215-222, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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