22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems-On-Chip Rome, Italy September 26-September 28 ISBN: 0-7695-2885-6
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFT.2007.35
Reliability issues play a relevant role in the design of embedded systems for critical ap- plications; this and the always increasing performance requirements lead to the adoption of new architectural solutions, as shown by the introduction of Multi-Processor Systems-on- Chip (MPSoC). MPSoCs raise new challenges related to the complexity of the interactions among several independent cores. This paper presents a framework, based on a simulation platform, for the design of this kind of embedded systems; the framework supports the use of reliability techniques in order to address fault detection and tolerance issues. The simu- lation platform is also adopted for a reliability assessment task, achieved by exploiting fault injection targeting each component of the system and by monitoring the effects on the entire architecture.
Citation:
G. Beltrame, C. Bolchini, L. Fossati, A. Miele, D. Sciuto, "A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems-On-Chip," dft, pp.132-142, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||