RAM-based fault tolerant state machines for FPGAs

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	Similar Articles Articles by Laura Frigerio Articles by Fabio Salice

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)

Rome, Italy

September 26-September 28

ISBN: 0-7695-2885-6

	ASCII Text	x
	Laura Frigerio, Fabio Salice, "RAM-based fault tolerant state machines for FPGAs," Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on, pp. 312-320, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007.

	BibTex	x
	@article{ 10.1109/DFT.2007.33, author = {Laura Frigerio and Fabio Salice}, title = {RAM-based fault tolerant state machines for FPGAs}, journal ={Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on}, volume = {0}, year = {2007}, isbn = {0-7695-2885-6}, pages = {312-320}, doi = {http://doi.ieeecomputersociety.org/10.1109/DFT.2007.33}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on TI - RAM-based fault tolerant state machines for FPGAs SN - 0-7695-2885-6 SP312 EP320 A1 - Laura Frigerio, A1 - Fabio Salice, PY - 2007 KW - null VL - 0 JA - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on ER -

Laura Frigerio, Politecnico di Milano, Dip. di Elettronica e Informazione

Fabio Salice, Politecnico di Milano, Dip. di Elettronica e Informazione

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFT.2007.33

This paper presents a solution to protect FSM implemented on FPGAs from SEU, exploiting the embedded memories available in modern FPGA devices and a Hamming code for error detection and correction. A fault tolerant FSM architecture is presented, along with a generator to automate the FSM implementation. Experimental results show that this solution is particularly suited especially when FSMs with a large number of outputs are present in the target design.

Citation:

Laura Frigerio, Fabio Salice, "RAM-based fault tolerant state machines for FPGAs," dft, pp.312-320, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

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