22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) Timing-Aware Diagnosis for Small Delay Defects Rome, Italy September 26-September 28 ISBN: 0-7695-2885-6
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFT.2007.30
As semiconductor technologies progress, testing of small delay defects are becoming more important for SoCs. However, fault diagnosis of small delay defects has not been developed. We propose a novel timing-aware method for diagnosing small delay defects with a small computation cost using gate delay fault simulation with the minimum detectable delay, as introduced in the statistical delay quality model. The experimental results show that the proposed method is capable of identifying fault locations for small delay defects with a small computation cost.
Citation:
Takashi Aikyo, Hiroshi Takahashi, Yoshinobu Higami, Junichi Ootsu, "Timing-Aware Diagnosis for Small Delay Defects," dft, pp.223-234, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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