Checker Design for On-line Testing of Xilinx FPGA Communication Protocols

D
DFT
2007
22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)
Abstract - Checker Design for On-line Testing of Xilinx FPGA Communication Protocols

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22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)

Rome, Italy

September 26-September 28

ISBN: 0-7695-2885-6

	ASCII Text	x
	Martin Straka, Jiri Tobola, Zdenek Kotasek, "Checker Design for On-line Testing of Xilinx FPGA Communication Protocols," Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on, pp. 152-160, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007.

	BibTex	x
	@article{ 10.1109/DFT.2007.21, author = {Martin Straka and Jiri Tobola and Zdenek Kotasek}, title = {Checker Design for On-line Testing of Xilinx FPGA Communication Protocols}, journal ={Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on}, volume = {0}, year = {2007}, isbn = {0-7695-2885-6}, pages = {152-160}, doi = {http://doi.ieeecomputersociety.org/10.1109/DFT.2007.21}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on TI - Checker Design for On-line Testing of Xilinx FPGA Communication Protocols SN - 0-7695-2885-6 SP152 EP160 A1 - Martin Straka, A1 - Jiri Tobola, A1 - Zdenek Kotasek, PY - 2007 KW - null VL - 0 JA - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on ER -

Martin Straka, Brno University of Technology

Jiri Tobola, Brno University of Technology

Zdenek Kotasek, Brno University of Technology

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFT.2007.21

In the paper, a methodology of developing checkers for communication protocol testing is presented. It was used to develop checker to test IP cores communication protocol implemented in Xilinx FPGA based designs. A formal language enabling to describe the protocol was created for this purpose together with a generator of the formal description into VHDL code. The VHDL code can be then used for the synthesis of the checker structure and used in applications with Xilinx FPGAs.

Citation:

Martin Straka, Jiri Tobola, Zdenek Kotasek, "Checker Design for On-line Testing of Xilinx FPGA Communication Protocols," dft, pp.152-160, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

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