The growing dispersion of parameters in CMOS ICs poses relevant uncertainties on gate output conductances and logic thresholds that affect bridging fault (BF) detection. To analyze the quality of fault simulation and test generation tools using nominal IC parameters, we studied BF detection as a function of the standard deviation of parameters: results show that a single test vector cannot ensure acceptable escape probabilities. Conversely, the minimal number of test vectors providing null escape probability is upper-bounded with respect to variations of parameters, as verified by Monte Carlo electrical-level simulations. We propose a method to derive such minimal test sets for low frequency testing. A fault simulator and a test generator have been developed supporting the search of minimal test sets targeting a null escape probability.