During semiconductor manufacturing, particles undesirably depose on the surface of the wafer causing "open" and "short" defects to interconnects. In this paper, a third type of defects called "interconnect narrowing" defect is defined. Interconnect narrowing occurs when a defect intervenes the lithographic printing of interconnects causing the formation of a narrow interconnect. The narrow sites of defective interconnects favor electromigration that makes narrow interconnects more likely to induce a chip failure than regular interconnects. In this paper, a layout sensitivity model accounting for narrowing defects is derived. A methodology for predicting the probability of narrow interconnects using the sensitivity model is then proposed. The layout sensitivity model for narrow interconnects is tested and compared to actual and simulated data. Our layout sensitivity model for narrow interconnects predicts the probability of narrowing with 3.1% error, on average. The model is then combined with electromigration constraints to predict mean-time-to-failure of chips manufactured in future technology down to 32nm node. The paper concludes with some other possible applications of the narrow interconnect predictive model.