21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06) A Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Neural Network Arlington, Virginia, USA October 04-October 06 ISBN: 0-7695-2706-X
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFT.2006.8
This paper introduces an implementation method of multiple weight as well as neuron fault-tolerant multilayer neural networks. Their fault-tolerance is derived from our extended back propagation learning algorithm called the deep learning method. The method can realize a desired weight as well as neuron fault-tolerance in multilayer neural networks where weight values are floating-point and the sigmoid function is used to calculate neuron output values. In this paper, fault-tolerant multilayer neural networks are implemented as digital circuits where weight values are quantized and the step function is used to calculate neuron output values using the deep learning method, the VHDL notation, and the logic design software QuartusII of Altera Inc. The efficiency of our method is shown in terms of fabrication-time cost, hardware size, neural computing time, generalization property, and so on.
Index Terms:
multilayer neural network, fault tolerance, weight fault, neuron fault, VHDL, FPGA
Citation:
Tadayoshi Horita, Takurou Murata, Itsuo Takanami, "A Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Neural Network," dft, pp.554-562, 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06), 2006 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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