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21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06)
A Metric of Tolerance for the Manufacturing Defects of Threshold Logic Gates
Arlington, Virginia, USA
October 04-October 06
ISBN: 0-7695-2706-X
ASCII Text
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Sandeep Dechu, Manoj Kumar Goparaju, Spyros Tragoudas, "A Metric of Tolerance for the Manufacturing Defects of Threshold Logic Gates," Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on, pp. 318-326, 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06), 2006.
 
 
BibTex
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@article{ 10.1109/DFT.2006.7,
author = {Sandeep Dechu and Manoj Kumar Goparaju and Spyros Tragoudas},
title = {A Metric of Tolerance for the Manufacturing Defects of Threshold Logic Gates},
journal ={Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on},
volume = {0},
year = {2006},
issn = {1550-5774},
pages = {318-326},
doi = {http://doi.ieeecomputersociety.org/10.1109/DFT.2006.7},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
TI - A Metric of Tolerance for the Manufacturing Defects of Threshold Logic Gates
SN - 1550-5774
SP318
EP326
A1 - Sandeep Dechu,
A1 - Manoj Kumar Goparaju,
A1 - Spyros Tragoudas,
PY - 2006
KW - null
VL - 0
JA - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
ER -
 
Sandeep Dechu, Southern Illinois University Carbondale, USA
Manoj Kumar Goparaju, Southern Illinois University Carbondale, USA
Spyros Tragoudas, Southern Illinois University Carbondale, USA
Compared to CMOS logic gates, threshold logic gates are more susceptible to manufacturing inaccuracies. These inaccuracies may inadvertently affect the functionality of the gate. Hence it is very much important to consider the manufacturing defects during the design of gates using threshold logic principle. This paper defines a metric which indicates the degree of tolerance of a designed gate to the manufacturing inaccuracies. Experimental results have been presented for several gates.
Citation:
Sandeep Dechu, Manoj Kumar Goparaju, Spyros Tragoudas, "A Metric of Tolerance for the Manufacturing Defects of Threshold Logic Gates," dft, pp.318-326, 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06), 2006
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