21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06) VLSI Implementation of a Fault-Tolerant Distributed Clock Generation Arlington, Virginia, USA October 04-October 06 ISBN: 0-7695-2706-X
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFT.2006.67
In this paper we will introduce a novel approach for the on-chip generation of a faulttolerant clock. We will motivate why it becomes more and more desirable to provide VLSI circuits with fault-tolerant clocking methods and how this fault tolerance can be achieved. The proposed clock generation method is based on the adaptation of a well known distributed clock synchronization algorithm which has been adapted for hardware implementation. We will present the underlying algorithm, point out the difficulties for the hardware implementation and will provide a detailed description of the resulting VLSI implementation. To emphasize the feasibility of the proposed fault-tolerant clock generation method we also present some measurement results from a prototype implementatio
Citation:
M. Ferringer, G. Fuchs, A. Steininger, G. Kempf, "VLSI Implementation of a Fault-Tolerant Distributed Clock Generation," dft, pp.563-571, 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06), 2006 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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