21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06) A Built-In Redundancy-Analysis Scheme for Self-Repairable RAMs with Two-Level Redundancy Arlington, Virginia, USA October 04-October 06 ISBN: 0-7695-2706-X
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFT.2006.6
With the increasing demand of memories in system-on-chip (SOC) designs, developing efficient yieldimprovement techniques for memories becomes an important issue. Built-in self-repair (BISR) technique has become a popular method for repairing defective embedded memories. To allocate redundancy efficiently, builtin redundancy-analysis (BIRA) function is usually needed for designing a BISR scheme. This paper presents an efficient BIRA scheme for RAMs with two-level redundancy (i.e., spare rows, spare columns, and spare words). Experimental results show that the repair rate of the proposed BIRA scheme approximates to that of the exhaustive search with the same redundancy organization. Furthermore, the repair rate of the proposed BIRA scheme with two-level redundancy is higher than that of the exhaustive search scheme with one-level redundancy (i.e.,spare rows and spare columns). The area cost of the proposed BIRA scheme is low. For example, the hardware overhead of the proposed BIRA scheme for an 8K?64-bit RAM with three spare rows, three spare columns, and two spare words is only about 2%.
Citation:
Yu-Jen Huang, Da-Ming Chang, Jin-Fu Li, "A Built-In Redundancy-Analysis Scheme for Self-Repairable RAMs with Two-Level Redundancy," dft, pp.362-370, 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06), 2006 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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