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21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06)
Multi-Site and Multi-Probe Substrate Testing on an ATE
Arlington, Virginia, USA
October 04-October 06
ISBN: 0-7695-2706-X
Xiaojun Ma, Northeastern University, USA
Fabrizio Lombardi, Northeastern University, USA
This paper presents a novel method that utilizes multi-site and multi-probe facilities in an ATE for substrate testing. The test time for a batch can be considerably reduced by efficiently utilizing an ATE with a number of flying-probes and multiple substrates under test (SUTs). An analytical model that predicts very accurately the batch test time is proposed. This model establishes the optimal multisite configuration as corresponding to the batch size that allow multiple SUTs to be simultaneously tested on a ATE. Simulation results for an ATE with 12 flying-probe as example of a commercially available tester are provided; for this ATE the proposed method achieves a reduction of 54.66% in test time over a single-site method (at complete coverage of the modeled faults).
Index Terms:
substrate testing, ATE, multi-site, multi-probe, manufacturing test, MCM.
Citation:
Xiaojun Ma, Fabrizio Lombardi, "Multi-Site and Multi-Probe Substrate Testing on an ATE," dft, pp.495-506, 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06), 2006
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