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21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06)
Modified Triple Modular Redundancy Structure based on Asynchronous Circuit Technique
Arlington, Virginia, USA
October 04-October 06
ISBN: 0-7695-2706-X
ASCII Text
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Gong Rui, Chen Wei, Liu Fang, Dai Kui, Wang Zhiying, "Modified Triple Modular Redundancy Structure based on Asynchronous Circuit Technique," Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on, pp. 184-196, 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06), 2006.
 
 
BibTex
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@article{ 10.1109/DFT.2006.44,
author = {Gong Rui and Chen Wei and Liu Fang and Dai Kui and Wang Zhiying},
title = {Modified Triple Modular Redundancy Structure based on Asynchronous Circuit Technique},
journal ={Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on},
volume = {0},
year = {2006},
issn = {1550-5774},
pages = {184-196},
doi = {http://doi.ieeecomputersociety.org/10.1109/DFT.2006.44},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
TI - Modified Triple Modular Redundancy Structure based on Asynchronous Circuit Technique
SN - 1550-5774
SP184
EP196
A1 - Gong Rui,
A1 - Chen Wei,
A1 - Liu Fang,
A1 - Dai Kui,
A1 - Wang Zhiying,
PY - 2006
KW - null
VL - 0
JA - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
ER -
 
Gong Rui, National University of Defense Technology, P.R. China
Chen Wei, National University of Defense Technology, P.R. China
Liu Fang, National University of Defense Technology, P.R. China
Dai Kui, National University of Defense Technology, P.R. China
Wang Zhiying, National University of Defense Technology, P.R. China
Two modified Triple Modular Redundancy (TMR) structures based on asynchronous circuit technique are proposed in this paper. Double Modular Redundancy (DMR) structure uses asynchronous C element to output and keep the correct value of two redundant storage cells. Temporal Spatial Triple Modular Redundancy structure with DCTREG (TSTMR-D) uses explicit separated master and slave latch structure of de-synchronous pipeline. Three soft error tolerant 8051 cores with DMR, TMR and TSTMR-D respectively are implemented in SMIC 0.35?m process. Fault injection experiments are also included. The experiment results indicate that DMR structure has a relatively low overhead on both area and latency than TMR, while tolerances SEUs in sequential logic. TSTMR-D structure can tolerance soft errors in both sequential logic and combinational logic with reasonable area and latency overhead.
Citation:
Gong Rui, Chen Wei, Liu Fang, Dai Kui, Wang Zhiying, "Modified Triple Modular Redundancy Structure based on Asynchronous Circuit Technique," dft, pp.184-196, 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06), 2006
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