Low Power SoC Memory BIST

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	Similar Articles Articles by Yuejian Wu Articles by Andre Ivanov

21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06)

Arlington, Virginia, USA

October 04-October 06

ISBN: 0-7695-2706-X

	ASCII Text	x
	Yuejian Wu, Andre Ivanov, "Low Power SoC Memory BIST," Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on, pp. 197-205, 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06), 2006.

	BibTex	x
	@article{ 10.1109/DFT.2006.39, author = {Yuejian Wu and Andre Ivanov}, title = {Low Power SoC Memory BIST}, journal ={Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on}, volume = {0}, year = {2006}, issn = {1550-5774}, pages = {197-205}, doi = {http://doi.ieeecomputersociety.org/10.1109/DFT.2006.39}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on TI - Low Power SoC Memory BIST SN - 1550-5774 SP197 EP205 A1 - Yuejian Wu, A1 - Andre Ivanov, PY - 2006 KW - null VL - 0 JA - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on ER -

Yuejian Wu, Nortel, Canada

Andre Ivanov, Univ. of British Columbia, Canada

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFT.2006.39

With the ever increasing number of memories embedded in a System-on-Chip (SoC), power dissipation due to test has become a serious concern. This paper studies power dissipation in SRAMs and proposes a novel low power memory BIST. Its effectiveness is evaluated on memories in 130 and 90 nm technologies. As demonstrated, up to 30% power reduction can be achieved with virtually zero hardware overhead.

Citation:

Yuejian Wu, Andre Ivanov, "Low Power SoC Memory BIST," dft, pp.197-205, 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06), 2006

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